The present invention relates to a semiconductor integrated circuit and particularly to a semiconductor integrated circuit using MOS transistors.
In recent years, high integration and low power consumption have been promoted in various kinds of semiconductor integrated circuits. In a semiconductor integrated circuit, there is a threshold voltage Vt for determining the on-off characteristic of an MOS transistor. The threshold voltage Vt must be lowered to improve drivability to thereby improve the operating speed of the circuit. Even in the case where the internal supply voltage Vdd of the circuit is lowered, the threshold voltage Vt needs to be set to be small in order to keep the operating speed high.
Lowering of the threshold voltage Vt, however, incurs a problem that the power consumption of the semiconductor integrated circuit increases greatly due to rapid increase of leakage current as described in 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46.
To prevent this problem, there is proposed a semiconductor integrated circuit in which the substrate bias voltage is changed according to the operating mode, such as a stand-by mode, an active mode, or the like, to thereby control the threshold voltage of an MOS transistor, in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 166-167, 1996.
On the other hand, there is a further proposal in which real and virtual power supply lines are provided so as to be linked by switching MOS transistors so that main circuits are supplied with power through the virtual power supply lines but the switching MOS transistors are turned off in the stand-by mode to prevent the main circuits from being supplied with power to thereby achieve reduction of power consumption, in IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995. Increase of the leakage current is, however, unavoidable for high-speed operation in the active mode even in the case where these background-art techniques are used.
FIGS. 24A and 24B show three stages of inverters as an example of background-art circuit. FIG. 24A shows an equivalent circuit configuration. FIG. 24B shows a specific circuit configuration. When, for example, node O1 is at an xe2x80x9cLxe2x80x9d level in the stand-by mode, node O3 is at an xe2x80x9cLxe2x80x9d level and nodes O2 and O4 are at an xe2x80x9cHxe2x80x9d level. In this case, with respect to the first and second stages of inverters, a leakage current flows through transistors Q1 and Q4. If the threshold voltage of the transistors is lowered, the leakage current increases greatly.
On the other hand, in accordance with JP-A-7-162288, there is a proposal in which time difference is provided between a signal supplied to an MOS transistor changed from OFF to ON and a signal supplied to an MOS transistor changed from ON to OFF so that the former signal is propagated earlier than the latter signal to thereby achieve high-speed operation without providing any change of the threshold voltage Vt. If the former signal is propagated earlier, it is, however, impossible to expect a greatly speeding-up effect as a whole because the latter signal is propagated later. The inventors"" examination has proved that the speeding-up effect is about 10% at the best.
In each of the background-art semiconductor integrated circuits, as described above, there was a problem that the leakage current in the active mode increased when the operating speed of the circuit was improved or kept high even when the internal supply voltage Vdd was lowered.
The present invention is configured in consideration of the aforementioned circumstances and it is an object thereof to provide a semiconductor integrated circuit in which not only power consumption caused by a leakage current in an active mode can be suppressed from increasing but also the circuit can operate at a high speed.
In order to achieve the above object, according to an aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second node; a second n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a second operating potential point; a third n-channel FET having a gate controlled by the first node and having a source-drain path connected between the second node and a third operating potential point; a second p-channel FET having a gate controlled by the first input and having a source-drain path connected between a third node and a fourth node; a third p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between the first operating potential point and the third node; a fourth p-channel FET having a gate controlled by the fourth node and having a source-drain path connected between a fourth operating potential point and the third node; and a fourth n-channel FET having a gate controlled by the second input and having a source-drain path connected between the fourth node and the second operating potential point.
According to another aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first p-channel FET having a gate controlled by a first input and having a source-drain path connected between a first operating potential point and a first node; a first n-channel FET having a gate controlled by a second input and having a source-drain path connected between the first node and a second operating potential point; a second n-channel FET having a gate controlled by the first operating potential point and having a source-drain path connected between the first node and the second operating potential point; a second p-channel FET having a gate controlled by the first node and having a source-drain path connected between the first operating potential point and the second node; a third n-channel FET having a gate controlled by the second input and having a source-drain path connected between the second node and the second operating potential point; and a third p-channel FET having a gate controlled by the second operating potential point and having a source-drain path connected between the first operating potential point and the second node.
According to a further aspect of the present invention, in view of the operation of an input signal, there is provided a semiconductor integrated circuit comprising a PMOS transistor (or a p-channel FET) and an NMOS transistor (an n-channel FET), wherein: a first signal is supplied to a gate of the PMOS transistor; a second signal is supplied to a gate of the NMOS transistor; and the first signal and the second signal are different from each other and satisfy the relations
PSxe2x89xa6NS less than PLxe2x89xa6NL
in which PL is the largest level of the first signal, PS is the smallest level of the first signal, NL is the largest level of the second signal, and NS is the smallest level of the second signal.
According to a further aspect of the present invention, there is provided a semiconductor integrated circuit comprising a PMOS transistor, and an NMOS transistor, wherein: a first signal is supplied to a gate of the PMOS transistor; a second signal is supplied to a gate of the NMOS transistor; and the first signal and the second signal are different from each other and levels PS, NS, NG, PG, PL and NL are arranged in order when the first signal changes between PL and PS, the second signal changes between NL and NS, PG is a gate input level serving as a threshold for turning on/off the PMOS transistor, and NG is a gate input level serving as a threshold for turning on/off the NMOS transistor.
Here, preferably, the difference between NG and NL is larger than the difference between NG and NS. Further, preferably, the difference between PG and PS is larger than the difference between PG and PL.
Specifically, the first signal has a rectangular waveform which changes between PL and PS; the second signal has a rectangular waveform (for example, pulse signal) which changes between NL and NS; and preferably, in view of easiness of control, the first signal is synchronized with the second signal both in leading edge timing and in trailing edge timing. That is, in-phase but different-waveform pulse signals are given to the gates of the PMOS and NMOS transistors respectively to control the PMOS and NMOS transistors. Specifically, the high and low levels of the PMOS transistor are different from those of the NMOS transistor. More specifically, the PMOS transistor is turned on at a trailing edge of the first signal; and the NMOS transistor is turned on at a leading edge of the second signal. In the present invention, there is no particular necessity to provide a time difference (phase difference) between the first and second signals.
The above configurations may be arranged into a suitable configuration such that a semiconductor integrated circuit comprises a PMOS transistor, and an NMOS transistor, wherein: a first pulse signal is supplied to a gate of the PMOS transistor; a second pulse signal is supplied to a gate of the NMOS transistor; HIGH of the first pulse signal is different from HIGH of the second pulse signal; LOW of the first pulse signal is different from LOW of the second-pulse signal; timing of changing the first pulse signal from HIGH to LOW is synchronized with timing of changing the second pulse signal from HIGH to LOW; and timing of changing the first pulse signal from LOW to HIGH is synchronized with timing of changing the second pulse signal from LOW to HIGH.
Further, specifically, the semiconductor integrated circuit further comprises a first circuit for generating the first pulse signal, and a second circuit for generating the second pulse signal, wherein: the first circuit includes PMOS and NMOS transistors having source-drain paths connected in series; and the second circuit includes PMOS and NMOS transistors having source-drain paths connected in series.
Further, specifically, the series connected source-drain paths of the PMOS and NMOS transistors of the first circuit are connected between a first potential and a first node; the series connected source-drain paths of the PMOS and NMOS transistors of the second circuit are connected between a second potential and a second node; either one of the second potential and a third potential is supplied to the first node through a first selector; and either one of the first potential or a fourth potential is supplied to the second node through a second selector.
A circuit layout suitable for achieving these circuits is as follows. Arranging a first wiring for feeding a first electric potential, a second wiring for feeding a second electric potential, a third wiring for feeding a third electric potential and a fourth wiring for feeding a fourth electric potential in parallel with one another is desirable for a compact circuit configuration. These wirings may be arranged in one metal wiring layer. If the increase of the area for these wirings is disliked, these wirings may be formed in different metal wiring layers and the metal wiring layers may be laminated vertically.
Further, the present invention may be used in combination with a technique of controlling the substrate bias voltage of transistors to change the threshold voltage of the transistors to thereby reduce the subthreshold leakage current. For this reason, there are required a fifth wiring for supplying the substrate bias potential of the PMOS transistor and a sixth wiring for supplying the substrate bias potential of the NMOS transistor. As a layout of these wirings, these wirings (from the first wiring to the sixth wiring) can be arranged in parallel with one another. These wirings may be formed in one metal wiring layer. If there is room to provide any other metal wiring layer, these wirings may be formed in different metal wiring layers and the metal wiring layers may be piled up vertically so that the area of the circuit can be reduced.
Further, when these wirings (from the first wiring to the sixth wiring) are classified into first and second groups by threes so that a plurality of cells each containing at least one of the first and second circuits and PMOS and NMOS transistors are arranged between the first and second groups, a regular cell layout can be achieved. Wirings for supplying substrate bias potentials may be omitted. In this case, these wirings are classified into two groups by twos so that cells are arranged between the two groups.
The present invention can be configured so that circuits according to the present invention are suitably mixed with background-art circuits. A typical example is a semiconductor integrated circuit composed of a logic block having a calculating function, and a memory block having a memory function. Circuits (for example, shown in FIG. 1) including the first and second circuits, and PMOS and NMOS transistors according to the present invention can be arranged in the inside of the logic block.
Alternatively, there is provided a semiconductor integrated circuit comprising a first circuit block and a second circuit block, wherein: the first circuit block includes circuit cells containing PMOS and NMOS transistors; a first pulse signal is supplied to gates of the PMOS transistors; a second pulse signal is supplied to gates of the NMOS transistors; HIGH of the first pulse signal is different from HIGH of the second pulse signal; LOW of the first pulse signal is different from LOW of the second pulse signal; timing of changing the first pulse signal from HIGH to LOW is synchronized with timing of changing the second pulse signal from HIGH to LOW; and timing of changing the first pulse signal from LOW to HIGH is synchronized with timing of changing the second pulse signal from LOW to HIGH.
Specifically, the first circuit block includes a first circuit for generating the first pulse signal, and a second circuit for generating the second pulse signal, the first circuit including PMOS and NMOS transistors having source-drain paths connected in series; and the second circuit including PMOS and NMOS transistors having source-drain paths connected in series.
Further, specifically, the series connected source-drain paths of the PMOS and NMOS transistors of the first circuit are connected between a first potential and a first node; the series connected source-drain paths of the PMOS and NMOS transistors of the second circuit are connected between a second potential and a second node; either one of the second potential and a third potential is supplied to the first node through a first selector; and either one of the first potential and a fourth potential is supplied to the second node through a second selector.
To achieve the aforementioned circuit configuration, the first wiring for feeding the first electric potential, the second wiring for feeding the second electric potential, the third wiring for feeding the third electric potential and the fourth wiring for feeding the fourth electric potential are arranged in the first circuit block so as to be parallel with one another.
On the other hand, a background-art circuit configuration is applied to the second circuit block. That is, the first and second wirings are arranged in the second circuit block so as to be parallel with each other but the third and fourth wirings are not arranged in the second circuit block. If the circuits according to the present invention and the background-art circuits are classified into blocks, wiring space can be saved so that efficient circuit arrangement can be made.